Past Events

CadenceTECHTALK: High-Speed SerDes Design, Analysis, and Optimization – Getting to 112Gbps

Join us for this webinar as we highlight the workflow required to overcome the new challenges associated with 112G, discuss some common design challenges and why end-to-end validation for sign-off is becoming ever more important and how Cadence integrated design and analysis technology provides a unique and powerful solution.

TSMC 2024 Europe Technology Symposium

Join us at the TSMC 2024 Europe Technology Symposium on May 14 to learn how Cadence and TSMC are partnering to deliver new technologies designed with Cadence.

CadenceCONNECT: Jasper User Group India 2024

Join us for our annual CadenceCONNECT: Jasper User Group India (previously known as Club Formal) on May 14 in Bangalore. This interactive, in-depth technical conference connects designers, verification engineers, and engineering managers to share the latest design and verification practices based on Cadence® Jasper formal verification technologies and methodologies. The CadenceCONNECT: Jasper User Group India has become the premier industry event for formal experts and beginners alike to learn from each other how to effectively accelerate their design and validation processes by applying formal methods.

ChipEx2024

Come and meet with our experts to discuss and learn more about Cadence Tensilica at ChipEX2024 exhibition; the annual event of the chip industry in Israel.

CadenceCONNECT: System Analysis Seminar (Taiwan)

因應AI新應用 Cadence 擴展電子系統設計新技術，本次於2024年5月7日舉辦「Cadence 系統設計分析暨PCB 設計研討會」上，將解鎖全新AI 數位雙生設計平台、AI驅動多物理場電磁模擬、生成式AI優化電子系統設計、助力Datacenter散熱設計與分析效能、PCB設計新架構等創新與趨勢話題，AI與EDA工具的交會，如何加速設計產品與開發，協助解決客戶的關鍵痛點!本次活動歡迎報名參與，期待跟各位見面交流！

On Demand CadenceTECHTALK: Introducing Cadence Reality DC Digital Twin Platform for Data Centers

Join this webinar to meet Cadence’s comprehensive digital twin solution that facilitates sustainable data center design and modernization, marking a significant leap forward in optimizing data center efficiency and operational capacity.

STAC Summit 2024 - London

Join Michael O'Sullivan, Engineering Director, Cadence in his presentation at the STAC Summit, as he will discuss "Staying cool at speed: Adding 25G to HFT accelerators".

CXL DevCon 2024

Visit Cadence at the first Compute Express Link (CXL®) DevCon. DevCon is a unique opportunity to participate in CXL technical training, view available products and technology demonstrations, and network with industry peers.

CadenceTECHTALK: Unleash Performance, Save Power: Mastering Processor Customization with the TIE Language

Join us for an engaging webinar where we'll show you how to turbocharge performance and minimize power consumption by harnessing the power of custom instructions using the TIE language. Don't miss out on this opportunity to optimize your processors like never before!

CadenceCONNECT: Automotive Solution Seminar

Cadence年度車用技術方案研討會將介紹新一代智慧車用電子晶片設計全流程解決方案，為複雜且耗時的車用晶片開發之路提供亟需的先機，加速整體車用功能安全晶片的開發。本次研討會特別邀請到第三方公正機構領導者SGS台灣檢驗科技公司蒞臨演說，介紹車用電子產業解決方案，如何協助汽車電子零組件的可靠度國際標準測試，滿足當今車用產業迫切的測試需求。席位有限，機會難得，敬請把握!