Past Events

CXL DevCon 2024

Visit Cadence at the first Compute Express Link (CXL®) DevCon. DevCon is a unique opportunity to participate in CXL technical training, view available products and technology demonstrations, and network with industry peers.

CadenceTECHTALK: Unleash Performance, Save Power: Mastering Processor Customization with the TIE Language

Join us for an engaging webinar where we'll show you how to turbocharge performance and minimize power consumption by harnessing the power of custom instructions using the TIE language. Don't miss out on this opportunity to optimize your processors like never before!

CadenceCONNECT: Automotive Solution Seminar

Cadence年度車用技術方案研討會將介紹新一代智慧車用電子晶片設計全流程解決方案，為複雜且耗時的車用晶片開發之路提供亟需的先機，加速整體車用功能安全晶片的開發。本次研討會特別邀請到第三方公正機構領導者SGS台灣檢驗科技公司蒞臨演說，介紹車用電子產業解決方案，如何協助汽車電子零組件的可靠度國際標準測試，滿足當今車用產業迫切的測試需求。席位有限，機會難得，敬請把握!

ARMMS Conference 2024

Come and visit Cadence at our exhibition space from April 29-30 to discuss circuit, system, thermal, PCB and EM simulation for RF/microwave product development.

D&R IP-SoC Silicon Valley

Cadence is a sponsor of D&R IP-SoC Silicon Valley. Don't miss Pulin Desai's presentation, Addressing Tomorrow's Automotive Compute Needs with Cadence at 1:00pm PT.

CadenceTECHTALK: Seamless SI/PI Signoff of Allegro PCB Designs Driven by In-Design Analysis(Taiwan)

In this Webinar, we will discuss how to design serial links (SerDes), DDR memory interface and power supply design, etc., using Sigrity Aurora with Topology explorer, System SI to design Conduct signal/power quality analysis in the different stages, and empowers EEs to create successful products on time and on budget. This webinar will be conducted in Mandarin.

CadenceTECHTALK: Design, Simulate, and Validate Your Circuit With PSpice

Introduction to best-in-class functional simulation environment and ecosystem powered by PSpice. PSpice and OrCAD X Capture combine to provide industry-leading, schematic entry, native analog, mixed-signal, and analysis engines to deliver a complete circuit simulation and verification solution. Join us this week and learn how to use PSpice to efficiently analyze the performance and operation of electronics.

DVClub Europe 2024 - Effective Adoption of Formal Verification

Join Alexandre Esselin Botelho, Sr Principal Application Engineer at Cadence, on April 23 at 13:00 BST in this demonstration of the current trends in methodology and ease-of-adoption features recently introduced in Jasper.

Cadence Cerebrus SaaS on AWS

Join the Cadence and AWS teams for an exciting hands-on workshop and networking event to learn about the Cadence Cerebrus SaaS on AWS. The new Cadence Cerebrus SaaS on AWS offers unlimited AWS compute and Cadence Cerebrus license capacity in a pay-for-use model. The result is superior PPA, quicker time-to-tapeouts, and cost-efficiency. Join the R&D team behind Cadence Cerebrus AI technology for a fun day of networking, food and prizes!

CadenceTECHTALK: Verisium SimAI: Coverage Gaps Meet Their Match (Taiwan)

This webinar will discuss addressing coverage gaps using new Verisium SimAI technology with the Cadence Xcelium Logic Simulator, the ultimate breakthrough in accelerating verification closure. Join us on April 23 to learn how a combination of Verisium, Xcelium, and Jasper Apps can quickly, efficiently, and automatically eliminate coverage holes and minimize the coverage closure gap. This webinar will be conducted in Mandarin.